1. Field of the Invention
This invention relates to the field of integrated circuit technology, and in particular to the testing of integrated circuits.
2. Description of Related Art
The testing of integrated circuits, particularly at high frequency, is becoming increasingly more complex, and therefore more costly. Test equipment must be continually upgraded and enhanced to include capabilities for testing devices that typically include the latest state-of-the-art technology.
FIG. 1 illustrates an example test system 100 comprising automated test equipment (ATE) 110 that is coupled to a device-under-test (DUT) 150 via a probe card 140. The ATE 110 typically includes a set of core test components 120, and special purpose test modules 130. In the example of FIG. 1, the system 100 is configured to enable testing of high-speed multimedia devices, using, for example, special purpose audio and video modules in the set of test modules 130. If the system 100 is used to test communications devices, the set of test modules 130 may contain, for example, discrete Fourier transform (DFT) modules, and other modules particular to communications devices. As the technologies used in the development of new devices 150 are advanced, the test modules 130 must be upgraded to keep pace with these advancements.
One of the particular problems associated with the testing of high-speed devices is the communication of signals to and from the device-under-test 150, particularly in the case of wafer-level testing. Long lead lines 111 from the test equipment 110 to the device-under-test 150 add capacitive and inductive loads to the driving signals. This additional load introduces a delay or mis-shaping of signals to and from the device-under-test 150. In many instances, certain tests cannot be performed xe2x80x98at device speedxe2x80x99, due to the distortions introduced by the long lead lines 111. Often, because the test system 100 is limited by the available test modules 130, the length of the leads 111, and other factors, tests are designed to correspond to the capabilities of the test system 100, rather than to the capabilities of the device-under-test 150. Additionally, because both the length and placement of the lines 111 affect the high-frequency characteristics of the lead lines 111, substantial time is often consumed to experiment with the mechanical setup. During testing, substantial time is often consumed in determining whether an observed anomalous behavior is caused by a problem in the device-under-test 150, or a problem in the test setup.
EP 0755071 teaches an alternative technique where the test system 100 is replaced by a special purpose integrated circuit that is configured to directly contact bonding pads on the device-under-test 150, as illustrated in FIG. 2. This special purpose integrated circuit 201 includes xe2x80x9csolder-bumpxe2x80x9d contacts 205 that are configured to contact corresponding contact pads 240 on the device-under-test 150.
As taught in the referenced patent, the probe card 140 is configured to effect the testing of the device-under-test 150, using test circuitry 202 in the integrated circuit 201, thereby eliminating the need for the test equipment 110 of FIG. 1. In accordance with this referenced patent, the special purpose integrated circuit 201 receives power 203 from an external source to power the test circuitry 202, and includes a light emitting diode (LED) that indicates whether the device-under-test 150 is defective. Because the test circuitry 202 is designed to be a stand-alone device that is capable of determining whether or not the device-under-test 150 is defective, without reliance upon the automatic test equipment 110 of FIG. 1, the design of the test circuitry 202 can be expected to be a complex and time consuming process. Additionally, because the test circuitry 202 is designed to test a particular device 150, the design and fabrication costs for the integrated circuit 201 cannot be allocated among a variety of devices.
It is an object of this invention to provide a test system that minimizes the adverse affects caused by long lead lines between automated test equipment and a device-under-test. It is a further object of this invention to provide a test architecture that facilitates the testing of a variety of devices. It is a further object of this invention to provide a preconditioning integrated circuit that is configurable for use in the testing of a variety of devices.
These objects and others are achieved by a test system that includes a preconditioning integrated circuit that is coupled between automatic test equipment (ATE) and a device-under-test (DUT). The preconditioning integrated circuit is configured to precondition signals that are communicated to and from the device-under-test, and particularly, to precondition high-frequency signals so as to avoid the adverse affects caused by long lead lines between the automated test equipment and the device-under-test. The preconditioning integrated circuit is designed to provide direct contact with the device-under-test, thereby providing very short lead lines to the device-under-test. High-frequency signals that are communicated to the device-under-test are generated, or reformed, at the preconditioning integrated circuit, based on control signals, or other test signals, from the automated test equipment. High-frequency, or time-critical, signals that are received from the device-under-test are processed and/or reformed by the preconditioning integrated circuit, for subsequent transmission to the automated test equipment.